@article {Katevenis201858,
	title = {Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development},
	journal = {Microprocessors and Microsystems},
	volume = {61},
	year = {2018},
	note = {cited By 0},
	pages = {58-71},
	doi = {10.1016/j.micpro.2018.05.009},
	url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-85048510982&doi=10.1016%2fj.micpro.2018.05.009&partnerID=40&md5=65dce9865ed4adbf8eca824478261a73},
	author = {Katevenis, M. and Ammendola, R. and Biagioni, A. and Cretaro, P. and Frezza, O. and Lo Cicero, F. and Lonardo, A. and Martinelli, M. and Paolucci, P.S. and Pastorelli, E. and Simula, F. and Vicini, P. and Taffoni, G. and Pascual, J.A. and Navaridas, J. and Luján, M. and Goodacre, J. and Lietzow, B. and Mouzakitis, A. and Chrysos, N. and Marazakis, M. and Gorlani, P. and Cozzini, S. and Brandino, G.P. and Koutsourakis, P. and Ruth, J.V. and Zhang, Y. and Kersten, M.}
}
